參數(shù)資料
型號(hào)： HYB314100BJL-50
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
中文描述： 4M X 1 FAST PAGE DRAM, 50 ns, PDSO20
封裝： 0.300 INCH, PLASTIC, SOJ-20
文件頁(yè)數(shù)： 10/23頁(yè)
文件大?。?/td> 1153K
代理商： HYB314100BJL-50
Semiconductor Group
10
HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS =
V
IL
. In the case of
I
CC4
it can be changed once or less during
a fast page mode cycle (
t
PC
).
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 5 ns.
7)
V
and
V
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
8) Measured with the specified current load and 100 pF at
V
OL
= 0.8 and
V
OH
= 2.0 V.
9) Operation within the
t
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only: If
t
RCD
is greater than the specified
t
RCD (max.)
t
CAC
.
10)Operation within the
t
RAD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only: If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11)Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
defines the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels.
13)
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and the data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
>
t
,
t
>
t
,
t
>
t
and
t
CPWD
>
t
CPWD (min.)
, the cycle is a read-write cycle and DO will contain data read from the selected cells. If neither
of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.
14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
相關(guān)PDF資料
PDF描述
HYB314100BJL-60 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
HYB314100BJL-70 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
HYB 314175BJ-50 3.3V 256 K x 16-Bit EDO-DRAM(3.3V 256K×16位 外延式數(shù)據(jù)輸出（EDO)動(dòng)態(tài)RAM)
HYB314175BJ-50- High-Speed Fully-Differential Amplifiers 8-MSOP-PowerPAD -40 to 85
HYB314175BJ-55 High-Speed Fully-Differential Amplifiers 8-MSOP-PowerPAD -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB314100BJL-60 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
HYB314100BJL-70 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
HYB314171BJ-50 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB314171BJ-50- 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
HYB314171BJ-60 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
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