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參數(shù)資料
| 型號： | HYB25R72180C-750 |
| 英文描述： | RAMBUS DRAM |
| 中文描述： | Rambus的內(nèi)存 |
| 文件頁數(shù)： | 9/76頁 |
| 文件大小： | 1218K |
| 代理商： | HYB25R72180C-750 |
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2002-05-06
Page
9
of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-
ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-
tion.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
Read or
W
rite command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
W
hen a Read or
W
rite command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai
when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed burst length applies to both Read
and
W
rite bursts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128400AT-8 | ?128Mb (32Mx4) DDR200 (2-2-2)? |
| HYB25D128800AT-7 | ?128Mb (16mx8) DDR266A (2-3-3)? |
| HYB25D128800AT-8 | ?128Mb (16Mx8) DDR200 (2-2-2)? |
| HYB25D128800T-7 | ?128Mb (16Mx8) DDR 266A (2-3-3)? |
| HYB25D128800T-7.5 | ?128Mb (16Mx8) DDR 266B (2.5-3-3)? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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