參數(shù)資料
型號: HYB25D256800BT-6
英文描述: ?256Mbit (32Mx8) DDR333 (2.5-3-3)?
中文描述: ?的256Mbit(32Mx8)DDR333內(nèi)存(2.5-3-3)?
文件頁數(shù): 45/76頁
文件大?。?/td> 1218K
代理商: HYB25D256800BT-6
2002-05-06
Page 45 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Truth Table 2: Clock Enable (CKE)
1. CK
E
n is the logic state of CK
E
at clock edge n: CK
E
n-1 was the state of CK
E
at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMA
N
D n is the command registered at clock edge n, and ACTIO
N
n is a result of COMMA
N
D n.
4. All states and sequences not shown are illegal or reserved.
Current State
CK
E
n-1
CK
E
n
Command n
Action n
N
otes
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
Self Refresh
L
H
Deselect or
N
OP
E
xit Self-Refresh
1
Power Down
L
L
X
Maintain Power-Down
Power Down
L
H
Deselect or
N
OP
E
xit Power-Down
All Banks Idle
H
L
Deselect or
N
OP
Precharge Power-Down
E
ntry
All Banks Idle
H
L
AUTO R
E
FR
E
S
H
Self Refresh
E
ntry
Bank(s) Active
H
L
Deselect or
N
OP
Active Power-Down
E
ntry
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 46
1. Deselect or
N
OP commands should be issued on any clock edges occurring during the Self Refresh
E
xit (t
X
S
N
R
) period. A mini-
mum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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