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| 型號： | HYB25D256800AT-7.5 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件頁數(shù)： | 47/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256800AT-7.5 |
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2002-05-06
Page 47 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
CS
RAS
CAS
WE
Command
Action
N
otes
Any
H
X
X
X
Deselect
N
OP/continue previous operation
1-6
L
H
H
H
N
o Operation
N
OP/continue previous operation
1-6
Idle
X
X
X
X
Any Command Otherwise
Allowed to Bank m
1-6
Row Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7
L
H
L
L
W
rite
Select column and start
W
rite burst
1-7
L
L
H
L
Precharge
1-6
Read
(Auto Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7
L
L
H
L
Precharge
1-6
W
rite
(Auto Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-8
L
H
L
L
W
rite
Select column and start new
W
rite burst
1-7
L
L
H
L
Precharge
1-6
Read (
W
ith
Auto Precharge)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7,10
L
H
L
L
W
rite
Select column and start
W
rite burst
1-7,
9
,10
L
L
H
L
Precharge
1-6
W
rite (
W
ith
Auto Precharge)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7,10
L
H
L
L
W
rite
Select column and start new
W
rite burst
1-7,10
L
L
H
L
Precharge
1-6
1. This table applies when CK
E
n-1 was
H
I
GH
and CK
E
n is
H
I
GH
(see Truth Table 2: Clock
E
nable (CK
E
) and after t
X
S
N
R /
t
X
SRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown
are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable).
E
xcep-
tions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active:
A row in the bank has been activated, and t
RCD
has been met.
N
o data bursts/accesses and no register
accesses are in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
W
rite:
A
W
rite burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge
E
nabled: See note 10.
W
rite with Auto Precharge
E
nabled: See note 10.
4. AUTO R
E
FR
E
S
H
and Mode Register Set commands may only be issued when all banks are idle.
5. A BURST T
E
RMI
N
AT
E
command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or
W
rites listed in the Command/Action column include Reads or
W
rites with Auto Precharge enabled and Reads or
W
rites
with Auto Precharge disabled.
8. Requires appropriate DM masking.
9
. A
W
rite command may be applied after the completion of data output.
10.
Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”.
W
hen a read with auto precharge or a write with auto precharge is enabled any
command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other
limitations apply (e.g. contention between R
E
AD data and
W
RIT
E
data must be avoided). The mimimum delay from a read or write
command with auto precharge enable, to a command to a different banks is summarized in table 4a.
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25D256800AT-8 | DDR Synchronous DRAM |
| HYB25D256800BC-7 | ?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
| HYB25D256800BT-5 | ?256Mbit (32Mx8) DDR400? |
| HYB25D256800BT-6 | ?256Mbit (32Mx8) DDR333 (2.5-3-3)? |
| HYB25D256800BT-7 | ?256Mbit (32Mx8) DDR266A (2-3-3)? |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800BC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256800BC-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
| HYB25D256800BC-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256800BC-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
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