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參數(shù)資料
| 型號： | HYB25D256400T-7.5 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件頁數(shù)： | 11/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400T-7.5 |
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2002-05-06
Page 11 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Notes:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the
block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within
the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access
within the block.
4.
W
henever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown in
Burst Definition
on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command
and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks.
If a Read command is registered at clock edge n, and the latency is
m
clocks, the data is available nominally
coincident with clock edge
n +
m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Burst Length
Starting Column Address
Order of Accesses
W
ithin a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
0
0-1
0-1
1
1-0
1-0
4
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400T-8 | DDR Synchronous DRAM |
| HYB25D256800AT-7 | ?256Mbit (32Mx8) DDR266A (2-3-3)? |
| HYB25D256800AT-7.5 | DDR Synchronous DRAM |
| HYB25D256800AT-8 | DDR Synchronous DRAM |
| HYB25D256800BC-7 | ?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400T-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (32Mx8) DDR266A (2-3-3)? |
| HYB25D256800AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800BC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
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