- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367357 > HYB25D256400BT-7 ?256Mbit (64Mx4) DDR266A (2-3-3)? PDF資料下載
參數(shù)資料
| 型號： | HYB25D256400BT-7 |
| 英文描述： | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
| 中文描述： | ？的256Mbit（64Mx4）DDR266A（2-3-3）？ |
| 文件頁數(shù)： | 57/76頁 |
| 文件大小： | 1218K |
| 代理商： | HYB25D256400BT-7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
2002-05-06
Page 57 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
IDD Current Measurement Conditions
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are changing once
per clock cycle. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2
*
tCK, tRAS = 5
*
tCK
Setup: A0
N
R0
N N
P0
N
Read : A0
N
R0
N N
P0
N
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N NN
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N N N
- repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are not
changing. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD= 3
*
tCK, Read with autoprecharge
Setup: A0
N
A1 R0 A2 R1 A3 R2
Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400BT-8 | ?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400T-7 | DDR Synchronous DRAM |
| HYB25D256400T-7.5 | DDR Synchronous DRAM |
| HYB25D256400T-8 | DDR Synchronous DRAM |
| HYB25D256800AT-7 | ?256Mbit (32Mx8) DDR266A (2-3-3)? |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400BT-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400BTL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BTL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BTL-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。