參數(shù)資料
型號： HYB25D256160BT-8
英文描述： ?256Mbit (16Mx16) DDR200 (2-2-2)?
中文描述： ？的256Mbit（16Mx16顯示）DDR200（2-2-2）？
文件頁數(shù)： 4/76頁
文件大小： 1218K
代理商： HYB25D256160BT-8
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 4 of 76
2002-05-06
Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock:
CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
CK
E
Input
Clock Enable:
CK
E H
I
GH
activates, and CK
E
Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CK
E
Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CK
E
is synchronous for power down entry and exit, and for self refresh entry. CK
E
is asyn-
chronous for self refresh exit. CK
E
must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CK
E
are disabled during power-down. Input
buffers, excluding CK
E
, are disabled during self refresh.
CS
Input
Chip Select:
All commands are masked when CS is registered
H
I
GH
. CS provides for exter-
nal bank selection on systems with multiple banks. CS is considered part of the command
code. The standard pinout includes one CS pin.
RAS, CAS,
WE
Input
Command Inputs:
RAS, CAS and
WE
(along with CS) define the command being entered.
DM
UDM, LDM
Input
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled
H
I
GH
coincident with that input data during a
W
rite access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to
the data on DQ8-DQ15.
BA0, BA1
Input
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read,
W
rite or Pre-
charge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or
E
MRS cycle.
A0 - A11
Input
Address Inputs:
Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/
W
rite commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LO
W
) or all banks (A10
H
I
GH
). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
DQ
Input/Output
Data Input/Output:
Data bus.
DQS
UDQS,LDQS
Input/Output
Data Strobe:
Output with read data, input with write data.
E
dge-aligned with read data, cen-
tered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on
DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15.
N
C
No Connect:
N
o internal electrical connection is present.
V
DDQ
Supply
DQ Power Supply:
2.5V
±
0.2V.
V
SSQ
Supply
DQ Ground
V
DD
Supply
Power Supply:
2.5V
±
0.2V.
V
SS
Supply
Ground
V
R
E
F
Supply
SSTL_2 reference voltage:
(V
DDQ
/ 2)
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相關代理商/技術參數(shù)
參數(shù)描述
HYB25D256160BTL-5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256MBit Double Data Rata SDRAM
HYB25D256160BTL-5A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256MBit Double Data Rata SDRAM
HYB25D256160BTL-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B
HYB25D256160BTL-7 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
HYB25D256160BTL-7F 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B
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