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參數(shù)資料
| 型號： | HYB25D128800AT-8 |
| 英文描述： | ?128Mb (16Mx8) DDR200 (2-2-2)? |
| 中文描述： | ？128Mb的（16Mx8）DDR200（2-2-2）？ |
| 文件頁數(shù)： | 16/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D128800AT-8 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 16 of 76
2002-05-06
as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any
Read or
W
rite commands being issued to that bank. A precharge command is treated as a
N
OP if there is no
open row in that bank, or if the previously open row is already in the process of precharging.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above,
but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in
con
j
unction with a specific Read or
W
rite command. A precharge of the bank/row that is addressed with the
Read or
W
rite command is automatically performed upon completion of the Read or
W
rite burst. Auto Pre-
charge is nonpersistent in that it is either enabled or disabled for each individual Read or
W
rite command.
Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge (t
RP
) is completed. This is determined as if
an explicit Precharge command was issued at the earliest possible time, as described for each burst type in
the Operation section of this data sheet.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-
cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Opera-
tion section of this data sheet.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a
refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t
Care” during an Auto Refresh command. The 128Mb DDR SDRAM requires Auto Refresh cycles at an aver-
age periodic interval of 15.6
μ
s (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system,
meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh
command is
9 *
15.6
μ
s. This maximum absolute interval is short enough to allow for DLL updates internal to
the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in t
AC
between
updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down.
W
hen in the self refresh mode, the DDR SDRAM retains data without external clocking. The
Self Refresh command is initiated as an Auto Refresh command coincident with CK
E
transitioning low. The
DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self
Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except
CK
E
(low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to
CK
E
returning high. Once CK
E
is high, the SDRAM must have
N
OP commands issued for t
X
S
N
R
because
time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply
N
OPs for 200 clock cycles before applying any other command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128800T-7 | ?128Mb (16Mx8) DDR 266A (2-3-3)? |
| HYB25D128800T-7.5 | ?128Mb (16Mx8) DDR 266B (2.5-3-3)? |
| HYB25D256160BT-8 | ?256Mbit (16Mx16) DDR200 (2-2-2)? |
| HYB25D256400AT-7 | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
| HYB25D256400AT-7.5 | DDR Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128800ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
| HYB25D128800CC-5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
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