參數(shù)資料
型號: HYB18T256800AFL-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbi t DDR2 SDRAM
中文描述: 256姆噸DDR2內(nèi)存
文件頁數(shù): 12/90頁
文件大?。?/td> 1711K
代理商: HYB18T256800AFL-3S
Page 12 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Block Diagram 4Mbit x 16 I/O x 4 Internal Memory Banks
(16Mb x 16 Organisation with 13 Row, 2 Bank and 9 Column External Addresses)
RAS
AP
CAS
CK
CS
WE
CK
C
Column-Address
Counter/Latch
Mode
Registers
9
C
D
A0-A12,
BA0, BA1
CKE
15
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(8192 x 128 x 64)
Sense Amplifiers
Bank1Bank2
Bank3
15
7
2
2
2
R
64
COL0
LDQ0-LDQ7
LDM
UDQ0-UDQ7
UDM
LDQS
LDQS
UDQS
UDQS
Column
Decoder
128
R
1
1
B
R
&
8192
A
B
15
R
1
DQS
DQS
CK, CK
DLL
16
16
16
16
16
Input
Register
2
2
2
2
2
64
8
64
Data
Mask
Data
CK,
CK
COL0,1
COL0,1
M
GDQS
2
2
16
64
R
Write
FIFO
Dr&
D
2
2
16
16
16
16
16
16
16
16
15
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation
of the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the
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