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參數(shù)資料
| 型號(hào)： | HYB18T256800AFL-37 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbi t DDR2 SDRAM |
| 中文描述： | 256姆噸DDR2內(nèi)存 |
| 文件頁(yè)數(shù)： | 50/90頁(yè) |
| 文件大?。?/td> | 1711K |
| 代理商： | HYB18T256800AFL-37 |
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Page 50 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.8.2 Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2
SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery
time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Pre-
charge from the completion of the write burst may be reactivated if the following two conditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
In DDR2 SDRAM’s the write recovery time delay (WR) has to be programmed into the MRS mode register. As
long as the analog twr timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles.
Minimum Write to Activate command spacing to the same bank =
WL + BL/2 + tDAL.
Examples:
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
NOP
NOP
NOP
NOP
NOP
Bank A
Activate
NOP
W RITE
w/AP
T0
T2
T1
T3
T4
T5
T6
T7
NOP
CMD
DQ
BW-AP223
A10 ="high"
tRP
Auto-Precharge Begins
DIN A0 DIN A1 DIN A2 DIN A3
WL = RL-1 = 2
WR
tRCmin.
>=tRASmin.
DQS,
DQS
Completion of the Burst Write
tDAL
CK, CK
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| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF) |
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