
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
INFINEON Technologies
19
2.04
32
Address and Command Setup Time (tIS)
-5
-3.7
-3
-5
-3.7
-3
-5
-3.7
-3
-5
-3.7
-3
all
-5
-3.7 & -3
all
0.60 ns
0.50 ns
0.45 ns
0.60ns
0.50 ns
0.45ns
0.40 ns
0.35 ns
0.30 ns
0.40 ns
0.35 ns
0.30 ns
15 ns
10 ns
7.5 ns
7.5 ns
not used
60
50
45
60
50
45
40
35
30
40
35
30
3C
28
1E
1E
00
00
3C
39
4B
80
23
1E
19
2D
28
23
0F
00
10
7E
tbd.
tbd.
C1
00
XX
XX
XX
XX
XX
FF
33
Address and Command Hold Time (tIH)
34
Data Input Setup Time (tDS)
35
Data Input Hold Time (tDH)
36
37
Write Recovery Time (tWR)
Internal Write to Read Command delay (tWTR)
38
39
40
41
Internal Read to Precharge delay (tRTP)
Not used
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
all
-5 & -3.7
-3
all
all
-5
-3.7
-3
-5
-3.7
-3
60 ns
57 ns
75 ns
8 ns
0.35 ns
0.30 ns
0.25 ns
0.45 ns
0.40 ns
0.35 ns
15.0 μs
see note 1
Revision 1.0
42
43
44
Min. Auto Refresh Command Cycle Time (tRFC)
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew (tDQSQmax.)
45
Read Data Hold Skew Factor (tQHS)
46
PLL Relock Time
Reserved for “Delta Temperature in SPD”
SPD Revision
Checksum for Bytes 0 - 62
47-61
62
63
-5
-3.7
-3
7D
tbd.
tbd.
B6
tbd.
tbd.
64
Manufacturers JEDEC ID Code
Not used
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
Manufacturer’s Specific Data
Open for Customer use
Note 1 : Will be used for future SPD Code Revisions. For details of “Delta Temperature in SPD” see JEDEC ballot JC-
42.5 Item # 1468.
INFINEON
not used
65-71
72
73-90
91-92
93-94
95-98
99-127
128-255
Year/Week Code
Serial Number
blank
blank
Byte#
Description
Speed
Grade
SPD Entry
Value
Hex Value
Note:
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
H
H
H