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參數(shù)資料
| 型號： | HYB18H256321BF-11 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| 中文描述： | 8M X 32 SYNCHRONOUS GRAPHICS RAM MODULE, 0.22 ns, PBGA136 |
| 封裝： | GREEN, PLASTIC, TFBGA-136 |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 1302K |
| 代理商： | HYB18H256321BF-11 |
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HYB18H256321BF
256-Mbit GDDR3
Internet Data Sheet
Rev. 0.80, 2007-09
09132007-07EM-7OYI
14
3.1.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations
that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the
two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
3.1.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
TABLE 6
Burst Definition
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
3.1.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
The two Mode Register setups support different CAS Latencies in terms of clock cycles. The mid-range-speed Mode Register
supports latencies from 7 to 14. The high-speed Mode Register supports latencies from 10 to 17. The active Mode Register
setup is selected by Bit0 of EMRS2.
3.1.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
Burst Length
Starting Column Address
Order of Accesses within a Burst
(Type = sequential)
A2 A1 A0
—
X
0
X
1
X
4
8
X
X
X
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18H256321BF-12 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-14 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H512321BF | 512-Mbit GDDR3 Graphics RAM |
| HYB18L128160BF | DRAMs for Mobile Applications 128-Mbit Mobile-RAM |
| HYB18L256160B | DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18H256321BF-11/12/14 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-12 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-14 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H512321BF | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:512-Mbit GDDR3 Graphics RAM |
| HYB18H512321BF-08/10 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:512-Mbit GDDR3 Graphics RAM |
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