參數資料
型號: HY64UD16322A-I
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM
中文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, BGA48
封裝: 6 X 8 MM, FBGA-48
文件頁數: 8/11頁
文件大?。?/td> 269K
代理商: HY64UD16322A-I
HY64UD16322A Series
8
Revision 1.1
May. 2003
Notes :
1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.
4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. /OE is continuously low (/OE=V
IL
)
6. Q(data out) is the invalid data.
7. Q(data out) is the read data of the next address.
8. tWHZ is defined as the time at which the outputs achieve the high impedance state.
It is not referenced to output voltage levels.
9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
ADD
/CS1
CS2
/UB, /LB
/WE
Data Out
Data In
Vih
tWC
tCW
tBW
tWP
tWR
(2)
Data Valid
tAW
tAS
High-Z
tDW
tDH
tWHZ
(3,8)
tOW
(6)
(7)
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
ADD
/CS1
CS2
/UB, /LB
/WE
Data Out
Data In
Vih
tWC
tCW
tBW
tWP
tWR
(2)
Data Valid
tAW
High-Z
tDW
tDH
High-Z
tAS
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