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參數(shù)資料
| 型號(hào)： | HY64UD16162M-DF70E |
| 英文描述： | PSEUDO-STATIC RAM|1MX16|CMOS|BGA|48PIN|PLASTIC |
| 中文描述： | 偽靜態(tài)內(nèi)存| 1MX16 |的CMOS | BGA封裝| 48PIN |塑料 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | HY64UD16162M-DF70E |
HY64UD16162M Series
7
Revision 1.7
March. 2002
Notes :
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status.
2. /OE = V
IL
3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state.
These are not referenced to output voltage levels.
4. /CS1 in high for the standby, low for active.
/UB and /LB in high for the standby, low for active.
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
ADD
/CS1
CS2
/UB, /LB
/OE
Data Out
High-Z
Vih
tRC
tAA
tACS
tBA
tOE
tOLZ
(3)
tBLZ
(3)
tCLZ
(3)
tOH
tCHZ
(3)
tBHZ
(3)
tOHZ
(3)
Data Valid
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
ADD
Data Out
Data Valid
tRC
Previous Data
tOH
tAA
tOH
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1
/UB, /LB
Data Out
Data Valid
High-Z
tCLZ
(3)
tACS
tCHZ
(3)
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| HY64UD16162M-DF70I | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1M x 16 bit Low Low Power 1T/1C Pseudo SRAM |
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| HY64UD16162M-DF85E | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:PSEUDO-STATIC RAM|1MX16|CMOS|BGA|48PIN|PLASTIC |
| HY64UD16162M-DF85I | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:1M x 16 bit Low Low Power 1T/1C Pseudo SRAM |
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