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參數(shù)資料
| 型號： | HY62WT08081E-DGC |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | HY62WT08081E Series 32Kx8bit CMOS SRAM |
| 中文描述： | HY62WT08081E系列32Kx8bit CMOS SRAM的 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 205K |
| 代理商： | HY62WT08081E-DGC |
HY62WT08081E Series
AC CHARACTERISTICS
Vcc = 5V
±
10%, T
A
= 0
°
C to 70
°
C (Normal) / -25
°
C to 85
°
C (Extended) / -40
°
C to 85
°
C (Industrial)
unless otherwise specified.
Symbol
Parameter
#
Rev 04 / May. 2001
5
-55
-70
Min.
Max.
Min.
Max.
Unit
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
WRITE CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
10
5
0
0
5
-
70
-
-
-
10
5
0
0
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
25
-
-
20
20
-
70
70
35
-
-
30
30
-
10
11
12
13
14
15
16
17
18
19
Vcc = 2.7~3.6V, T
A
= 0
°
C to 70
°
C (Normal) / -25
°
C to 85
°
C (Extended) / -40
°
C to 85
°
C (Industrial)
unless otherwise specified.
Symbol
Parameter
#
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
55
45
45
0
40
0
0
25
0
5
-
-
-
-
-
-
70
60
60
0
50
0
0
30
0
5
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
-
-
-
25
-
-
-
-70*
-85
Min.
Max.
Min
Max.
Unit
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
WRITE CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
70
-
-
-
10
5
0
0
5
-
85
-
-
-
10
5
0
0
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
35
-
-
30
30
-
85
85
45
-
-
30
30
-
10
11
12
13
14
15
16
17
18
19
Note * 70ns is available with 30pF test load
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
70
60
60
0
50
0
0
30
0
5
-
-
-
-
-
-
85
75
75
0
60
0
0
40
0
5
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
-
-
-
30
-
-
-
READ CYCLE
READ CYCLE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY62WT08081E-DGE | HY62WT08081E Series 32Kx8bit CMOS SRAM |
| HY62WT08081E-DGI | HY62WT08081E Series 32Kx8bit CMOS SRAM |
| HY62WT08081E-DPC | HY62WT08081E Series 32Kx8bit CMOS SRAM |
| HY62WT08081E-DPE | HY62WT08081E Series 32Kx8bit CMOS SRAM |
| HY62WT08081E-DPI | HY62WT08081E Series 32Kx8bit CMOS SRAM |
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