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參數(shù)資料
| 型號： | HY62V8200BLLT1-E |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | HY62V8200B Series 256Kx8bit CMOS SRAM |
| 中文描述： | HY62V8200B系列256Kx8bit CMOS SRAM的 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 187K |
| 代理商： | HY62V8200BLLT1-E |
Y62V8200B Series
DESCRIPTION
The HY62V8200B is a high speed, low power and
2M bit CMOS SRAM organized as 262,144 words
by 8bit. The HY62V8200B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particularly well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
Product
No.
(V)
HY62V8200B
3.0~3.6
HY62V8200B-E
3.0~3.6
HY62V8200B-I
3.0~3.6
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
Rev 06 / Apr. 2001
2
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup( LL-part )
-. 2.0V(min) data retention
Standard pin configuration
-. 32-sTSOPI-8X13.4, 32-TSOPI -8X20
(Standard and Reversed)
Operation
Current/Icc(mA)
Current(uA)
5
25
5
25
5
25
Voltage
Speed
(ns)
70/85/100
70/85/100
70/85/100
Standby
Temperature
(
°
C)
0~70
-25~85(E)
-40~85(I)
TSOP-I sTSOP-I
(Standard) (Standard)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name
Pin Function
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A17
Address Input
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(3.0V~3.6V)
Vss
Ground
MEMORY ARRAY
256K x 8
ROW
DECODER
S
W
D
B
I/O1
I/O8
C
C
L
A
A0
A17
/CS1
CS2
/WE
/OE
A11
/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
相關(guān)PDF資料 |
PDF描述 |
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| HY62V8200BLLT1-I | HY62V8200B Series 256Kx8bit CMOS SRAM |
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| HY62V8400LG | 512K X 8-bit CMOS SRAM |
| HY62V8400LP | 512K X 8-bit CMOS SRAM |
| HY62V8400LR2 | 512K X 8-bit CMOS SRAM |
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