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參數(shù)資料
| 型號： | HY62UF16101CSLT2-I-85 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 85 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 160K |
| 代理商： | HY62UF16101CSLT2-I-85 |
HY62UF16100C Series
Rev.02 /Jun. 00
4
AC CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = TA = 0
°C to 70°C / -40°C to 85°C(I), unless otherwise specified
-55
-70
-85
Min.
Max.
Min.
Max.
Min
Max.
1
tRC
Read Cycle Time
55
-
70
-
85
-
ns
2
tAA
Address Access Time
-
55
-
70
-
85
ns
3
tACS
Chip Select Access Time
-
55
-
70
-
85
ns
4
tOE
Output Enable to Output Valid
-
35
-
40
-
45
ns
5
tBA
/LB, /UB Access Time
-
35
-
40
-
45
ns
6
tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
ns
7
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
ns
8
tBLZ
/LB, /UB Enable to Output in Low Z
5
-
5
-
5
-
ns
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
30
ns
10
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
30
ns
11
tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
0
30
ns
12
tOH
Output Hold from Address Change
10
-
10
-
10
-
ns
13
tWC
Write Cycle Time
55
-
70
-
85
-
ns
14
tCW
Chip Selection to End of Write
50
-
60
-
70
-
ns
15
tAW
Address Valid to End of Write
50
-
60
-
70
-
ns
16
tBW
/LB, /UB Valid to End of Write
50
-
60
-
70
-
ns
17
tAS
Address Set-up Time
0
-
0
-
0
-
ns
18
tWP
Write Pulse Width
45
-
50
-
55
-
ns
19
tWR
Write Recovery Time
0
-
0
-
0
-
ns
20
tWHZ
Write to Output in High Z
0
20
0
25
0
30
ns
21
tDW
Data to Write Time Overlap
25
-
30
-
35
-
ns
22
tDH
Data Hold from Write Time
0
-
0
-
0
-
ns
23
tOW
Output Active from End of Write
5
-
5
-
5
-
ns
AC TEST CONDITIONS
TA = 0
°C to 70°C / -40°C to 85°C (I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
DOUT
1728 Ohm
CL(1)
1029 Ohm
VTM=2.8V
Note
1. Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
Symbol
Parameter
#
Unit
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