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參數(shù)資料
| 型號(hào)： | HY62U8400ALLR2-I |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 512Kx8bit CMOS SRAM |
| 中文描述： | 512Kx8bit CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | HY62U8400ALLR2-I |
HY62U8400A Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 1,2,4)
tRC
Rev 07 / Apr. 2001
5
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,2,4)
/CS
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
ADDR
tRC
/CS
tAA
tACS
tOH
Data Valid
High-Z
Data
Out
/OE
tOE
tCLZ
(3)
tOLZ
(3)
tCHZ
(3)
tOHZ
(3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY62U8400ALLT2 | 512Kx8bit CMOS SRAM |
| HY62U8400ALLT2-E | 512Kx8bit CMOS SRAM |
| HY62U8400ALLT2-I | 512Kx8bit CMOS SRAM |
| HY62UF08401C | High Speed, Super Low Power and 4Mbit Full CMOS SRAM |
| HY62UF08401C-DS(I) | High Speed, Super Low Power and 4Mbit Full CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY62U8400ALLT2 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLT2-E | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLT2-I | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62UF08401C | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:High Speed, Super Low Power and 4Mbit Full CMOS SRAM |
| HY62UF08401C-DS(I) | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:High Speed, Super Low Power and 4Mbit Full CMOS SRAM |
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