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參數(shù)資料
| 型號： | HY62U8400ALLG-E |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:22; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:12-35 RoHS Compliant: No |
| 中文描述： | 512Kx8bit CMOS SRAM的 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 180K |
| 代理商： | HY62U8400ALLG-E |
HY62U8400A Series
Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARATERISTIC
T
A
= 0
é
to 70
é
(Normal)/-25
°
C to 85
°
C (Extended) /-40
°
C to 85
°
C (Industrial), unless otherwise specified.
Symbol
Parameter
Test Condition
V
DR
Vcc for Data Retention
/CS > Vcc-0.2V,
V
IN
> Vcc-0.2V or V
IN
< 0.2V
I
CCDR
Vcc = 3.0V,
/CS>Vcc-0.2V,
V
IN
>Vcc-0.2V or V
IN
<0.2V
tCDR
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Notes:
1. Typical values are at the condition of T
A
= 25
°
C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
DATA RETENTION MODE
Rev 07 / Apr. 2001
7
Min
2.0
-
-
-
0
Typ
-
-
-
-
-
Max
-
20
30
30
-
Unit
V
uA
uA
uA
ns
LL
LL-E
LL-I
Data Retention Current
tRC(2)
-
-
ns
/CS
VDR
/CS > VCC-0.2V
tCDR
tR
VSS
2.7V
2.2V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY62U8400ALLG-I | 512Kx8bit CMOS SRAM |
| HY62U8400ALLR2 | 512Kx8bit CMOS SRAM |
| HY62U8400A | 512Kx8bit CMOS SRAM |
| HY62U8400ALLR2-I | 512Kx8bit CMOS SRAM |
| HY62U8400ALLT2 | 512Kx8bit CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY62U8400ALLG-I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLR2 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLR2-E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLR2-I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
| HY62U8400ALLT2 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx8bit CMOS SRAM |
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