參數(shù)資料
型號(hào): HY62KF08802B-SD
廠商: Hynix Semiconductor Inc.
英文描述: 1M x 8bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
中文描述: 1M × 8位2.7?3.6V的超低功耗FCMOS慢的SRAM
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 142K
代理商: HY62KF08802B-SD
HY62KF08802B Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
READ CYCLE 2 (Note 1,2,4)
tRC
Rev.00 / Jan.02
5
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out
READ CYCLE 3 (Note 1,2,4)
/CS1
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
CS2
Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/OE
tAA
tACS
tOE
tCLZ
(3)
tOLZ
(3)
tOH
tCHZ
(3)
tOHZ
(3)
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