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參數(shù)資料
| 型號： | HY628400ALLT2-55 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.400 INCH, TSOP2-32 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 182K |
| 代理商： | HY628400ALLT2-55 |
HY628400A Series
Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARATERISTIC
T
A
= 0
é
to 70
é
(Normal)/-25
°
C to 85
°
C (Extended) /-40
°
C to 85
°
C (Industrial), unless otherwise specified.
Symbol
Parameter
V
DR
Vcc for Data Retention
/CS > Vcc - 0.2V,
V
IN
> Vcc - 0.2V or V
IN
< Vss + 0.2V
I
CCDR
Vcc = 3.0V,
/CS1>Vcc - 0.2V,
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
tCDR
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Rev 07 / Apr. 2001
7
Test Condition
Min
2.0
-
-
-
-
0
Typ
-
-
-
-
-
-
Max
-
50
20
50
30
-
Unit
V
uA
uA
uA
uA
ns
L
LL
L-E/I
LL-E/I
Data Retention Current
tRC
(2)
-
-
ns
Notes:
1. Typical values are at the condition of T
A
= 25
°
C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
/CS
VDR
/CS > VCC-0.2V
tCDR
tR
VSS
4.5V
2.2V
DATA RETENTION MODE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY628400ALLT2-E | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALLT2-I | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALR2 | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALR2-E | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALR2-I | 512K x8 bit 5.0V Low Power CMOS slow SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY628400ALLT2-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628400ALLT2-85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628400ALLT2-E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALLT2-I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALR2 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512K x8 bit 5.0V Low Power CMOS slow SRAM |
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