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參數(shù)資料
| 型號： | HY628100ALLG |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 128Kx8bit CMOS SRAM的 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 128K |
| 代理商： | HY628100ALLG |
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 /Feb.99 Hyundai Semiconductor
HY628100A Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY628100A is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100A uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
Product
Voltage
No
(V)
HY628100A
5.0
Comment : 50ns is available with 30pF test load.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
- 32pin 525mil SOP
- 32pin 8x20mm TSOP-I(Standard)
Speed
(ns)
55/70/85
Operation
Current(mA)
10
Standby Current(uA)
L
1mA
100
Temperature
(
°
C)
0~70
LL
20
PIN CONNECTION
SOP TSOP-I(Standard)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CS2
/WE
NC
A7
I/O1
Vss
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
32
30
29
28
27
26
25
24
22
21
20
19
18
17
/OE
/CS1
DQ1
A9
A15
NC
A16
A7
A6
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name
Pin Function
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A16
Address Input
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(5.0V)
Vss
Ground
CS2
A16
C
A0
ROW DECODER
MEMORY ARRAY
1024x1024
S
O
I/O1
I/O8
A
/CS1
/OE
/WE
W
C
L
相關PDF資料 |
PDF描述 |
|---|---|
| HY628100ALLT1 | 128Kx8bit CMOS SRAM |
| HY628100AG | 128Kx8bit CMOS SRAM |
| HY628100ALG | 128Kx8bit CMOS SRAM |
| HY628100ALT1 | 128Kx8bit CMOS SRAM |
| HY628100AT1 | 128Kx8bit CMOS SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY628100ALLG-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628100ALLG-10I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628100ALLG-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628100ALLG-55I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628100ALLG-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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