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參數(shù)資料
| 型號： | HY62256ALT1-I |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 32Kx8bit CMOS SRAM |
| 中文描述： | 32Kx8bit CMOS SRAM的 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 820K |
| 代理商： | HY62256ALT1-I |
HYUNDAI ELECTRONICS AMERICA
HY62256A-I
32K x 8bit CMOS SRAM
TIMING INFORMATION
TIMING DIAGRAM
READ CYCLE 1
Note (READ CYCLE):
1. t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open
circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, t
CHZ
max. is less than t
CLZ
min.
both for a given device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
Note (READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= V
IL
.
3. /OE =V
IL
.
WRITE CYCLE 1 (/OE Clocked)
1 of 3
22/10/97 12:35
-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HY62256ALT1-I70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:32Kx8bit CMOS SRAM |
| HY62256AP-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AP-10I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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