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| 型號(hào)： | HY5W2A6CSF-H |
| 英文描述： | SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X2MX16 |的CMOS | BGA封裝| 54PIN |塑料 |
| 文件頁(yè)數(shù)： | 14/24頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | HY5W2A6CSF-H |
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HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
15
CKE Enable(CKE) Truth TABLE
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting power down mode, a NOP (or Device Deselect) command is required on the first
positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be
entered from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first
positive edge of clock after CKE goes high and is maintained for a minimum 200
μ
sec.
Current State
CKE
Command
Action
Notes
Previous
Cycle
H
L
Current
Cycle
X
H
CS
RAS CAS WE
BA0,
BA1
A11-
A0
Self Refresh
X
X
H
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh with Device
Deselect
Exit Self Refresh with No Oper-
ation
ILLEGAL
ILLEGAL
ILLEGAL
Maintain Self Refresh
INVALID
Power Down mode exit, all
banks idle
ILLEGAL
Maintain Power Down Mode
1
2
L
H
L
H
H
H
X
X
2
L
L
L
L
H
L
H
H
H
L
X
X
X
X
X
H
H
X
L
L
L
H
H
L
H
L
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
2
2
Power
Down
1
2
L
L
H
L
L
H
L
X
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Deep
Power
Down
INVALID
Deep Power Down mode exit
Maintain Deep Power Down
Mode
Refer to the idle State section
of the Current State Truth Table
3
1
5
All Banks Idle
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
L
L
L
X
H
H
X
L
H
L
L
L
H
X
L
L
L
L
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
H
X
X
L
Op Code
X
X
X
H
X
X
L
Op Code
X
X
X
X
X
X
3
3
L
L
L
Auto Refresh
Mode Register Set
Refer to the idle State section
of the Current State Truth Table
3
4
H
L
L
L
3
3
4
Entry Self Refresh
Mode Register Set
Power Down
Refer to operations of the Cur-
rent State Truth Table
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
4
Any State
other than
listed above
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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| HY5W2A6CSF-P | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x16 SDRAM |
| HY5W2A6CSF-S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
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| HY5W2B6DLFP-HE | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5W6B6DLF-HE | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
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