參數(shù)資料
型號(hào)： HY5S6B6DSFP-BE
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： DRAM
英文描述： 4Banks x1M x 16bits Synchronous DRAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 9 ns, PBGA54
封裝： 0.80 MM PITCH, LEAD FREE, FBGA-54
文件頁(yè)數(shù)： 2/27頁(yè)
文件大?。?/td> 368K
代理商： HY5S6B6DSFP-BE
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.3 / July 2004
2
HY5S6B6D(L/S)F(P)-xE
4Banks x1M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5S6B6D(L/S)F(P) is a 67,108,864bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 1,048,576x16.
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst
length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM
also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank,
1bank, 2banks, or all banks.
The Hynix HY5S6B6D(L/S)F(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Re-
fresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to au-
tomatically adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write
cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum power
reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off
alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout
flexibility.
FEATURES
Standard SDRAM Protocol
I
nternal 4bank operation
●
Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
●
LVCMOS compatible I/O Interface
●
Low Voltage interface to reduce I/O power
●
Low Power Features
- PASR(Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
●
Programmable CAS latency of 1, 2 or 3
●
Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead)
HY5S6B6D(L/S)FP : Lead Free
HY5S6B6D(L/S)F : Lead
ORDERING INFORMATION
Part Number
Clock Frequency
CAS
Latency
Organization
Interface
HY5S6B6D(L/S)F(P)-SE
105MHz
3
4banks x 1Mb x 16
LVCMOS
HY5S6B6D(L/S)F(P)-BE
66MHz
2
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