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參數(shù)資料
| 型號： | HY5PS1G831LF-E3 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM |
| 中文描述： | 128M X 8 DDR DRAM, 0.6 ns, PBGA68 |
| 封裝： | FBGA-68 |
| 文件頁數(shù)： | 8/33頁 |
| 文件大?。?/td> | 540K |
| 代理商： | HY5PS1G831LF-E3 |
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Rev. 1.2 / Dec 2006
8
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
-Continue-
PIN
TYPE
DESCRIPTION
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/Output
Data Strobe : Output with read data, input with write data. Edge aligned with read data, cen-
tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corre-
sponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled
via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may
be used in single ended mode or paired with optional complementary signals DQS,
LDQS,UDQS and RDQS to provide differential pair signaling to the system during both reads
and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of
EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of
EMRS(1)
x4 DQS
x8 DQS
x8 DQS, RDQS,
x16 LDQS and UDQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
NC
No Connect : No internal electrical connection is present.
V
DDQ
Supply
DQ Ground
VSSQ
Supply
DQ Power Supply : 1.8V +/- 0.1V
V
DDL
Supply
DLL Power Supply : 1.8V +/- 0.1V
V
SSDL
Supply
DLL Ground
VDD
Supply
Power Supply : 1.8V +/- 0.1V
V
SS
Supply
Ground
V
REF
Supply
Reference voltage for inputs for SSTL interface.
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