參數(shù)資料
型號： HY5PS1G831F
廠商： Hynix Semiconductor Inc.
英文描述： 1Gb DDR2 SDRAM
中文描述： 1G DDR2內(nèi)存
文件頁數(shù)： 9/33頁
文件大?。?/td> 540K
代理商： HY5PS1G831F
Rev. 1.2 / Dec 2006
9
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
2.1
Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to Vss
- 1.0 V ~ 2.3 V
V
1
VDDQ
Voltage on VDDQ pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
VDDL
Voltage on VDDL pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
V
IN
,
V
OUT
Voltage on any pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
T
STG
Storage Temperature
-55 to +100
°
C
1, 2
1. .
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.
Please refer to JESD51-2 standard.
Symbol
Parameter
Rating
Units
Notes
Toper
Operating Temperature
0 to 85
°
C
1,2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature
rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During
operation, the DRAM case temperature must be maintained between 0 ~ 85
°
C under all other specification parameters. However,
in some applications, it is desirable to operate the DRAM up to 95
°
C case temperature. Therefore 2 spec options may exist.
1) Supporting 0 - 85
°
C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature
options.
2) Supporting 0 - 85
°
C and being able to extend to 95
°
C with doubling auto-refresh commands in frequency to a 32 ms
period(tRFI=3.9us).
Note; Currently the periodic Self-Refresh interval is hard coded within the DRAM to a specificic value.
There is a migration plan to support higher temperature Self-Refresh entry via the control of EMRS(2) bit A7. However, since
Self-Refresh control function is a migrated process. For our DDR2 module user, it is imperative to check SPD Byte 49 Bit 0
to ensure the DRAM parts support higer than 85
°
C case temperature Self-Refresh entry.
1) if SPD Byte 49 Bit 0 is a “0” means DRAM does not support Self-Refresh at higher than 85
°
C, then system have to ensure
the DRAM is at or below 85
°
C
case temperature before initiating Self-Refresh operation.
2) if SPD Byte 49 Bit 0 is a “1” means DRAM supports Self-Refresh at higher than 85
°
C
case temperature, then system can
use register bit A7 at EMRS(2) control DRAM to operate at proper Self-Refresh rate for higher temperature. Please also
refer to EMRS(2) register definition section and DDR2 DIMM SPD definition for details.
2.
Maximum DC Ratings
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