參數(shù)資料
型號： HY5PS1G431LF-Y6
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 1Gb DDR2 SDRAM
中文描述： 256M X 4 DDR DRAM, PBGA68
封裝： FBGA-68
文件頁數(shù)： 17/33頁
文件大?。?/td> 540K
代理商： HY5PS1G431LF-Y6
Rev. 1.2 / Dec 2006
17
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
For purposes of IDD testing, the following parameters are to be utilized
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
Timing Patterns for 8 bank devices x4/8
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
DDR2-667
DDR2-533
DDR2-400
Parameter
5-5-5
4-4-4
3-3-3
Units
CL(IDD)
5
4
3
tCK
tRCD(IDD)
15
15
15
ns
tRC(IDD)
60
60
55
ns
tRRD(IDD)-x4/x8
7.5
7.5
7.5
ns
tRRD(IDD)-x16
9
10
10
ns
tCK(IDD)
3
3.75
5
ns
tRASmin(IDD)
45
45
40
ns
tRASmax(IDD)
70000
70000
70000
ns
tRP(IDD)
15
15
15
ns
tRFC(IDD)-256Mb
75
75
75
ns
tRFC(IDD)-512Mb
105
105
105
ns
tRFC(IDD)-1Gb
127.5
127.5
127.5
ns
tRFC(IDD)-2Gb
197.5
197.5
197.5
ns
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