參數(shù)資料
型號(hào): HY5PS12421LF
廠商: Hynix Semiconductor Inc.
英文描述: 512Mb DDR2 SDRAM
中文描述: 512Mb DDR2 SDRAM芯片
文件頁(yè)數(shù): 12/35頁(yè)
文件大小: 624K
代理商: HY5PS12421LF
Rev. 1.0 / Feb. 2005
12
1
HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
3.2.1 Input DC Logic Leve
l
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
Notes:
1.
2.
Input waveform timing is referenced to the input signal crossing through the V
REF
level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH(ac)
min for rising edges and the range
from V
REF
to V
IL(ac)
max for falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
3.
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH
(dc)
dc input logic high
V
REF
+ 0.125
V
DDQ
+ 0.3
V
V
IL
(dc)
dc input logic low
- 0.3
V
REF
- 0.125
V
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH
(ac)
ac input logic high
V
REF
+ 0.250
-
V
V
IL
(ac)
ac input logic low
-
V
REF
- 0.250
V
Symbol
Condition
Value
Units
Notes
V
REF
Input reference voltage
0.5 * V
DDQ
V
1
V
SWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
V
SWING(MAX)
delta TR
delta TF
V
REF
-
V
IL
(ac)
max
delta TF
Falling Slew =
Rising Slew =
V
IH
(ac)
min
- V
REF
delta TR
3.2 DC & AC Logic Input Levels
< Figure : AC Input Test Signal Waveform>
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