參數(shù)資料
型號(hào)： HY5PS12421F
廠商： Hynix Semiconductor Inc.
英文描述： 512Mb DDR2 SDRAM
中文描述： 512Mb DDR2 SDRAM芯片
文件頁(yè)數(shù)： 25/35頁(yè)
文件大?。?/td> 624K
代理商： HY5PS12421F
Rev. 1.0 / Feb. 2005
25
1
HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
Figure -- Data input (write) timing
DMin
DMin
DMin
D
D
D
V
IH
(ac)
V
IL
(ac)
V
IH
(ac)
V
IL
(ac)
V
IH
(dc)
V
IL
(dc)
V
IH
(dc)
V
IL
(dc)
t
CH
t
CL
CK
CK
CK/CK
DQS/DQS
DQ
DQS
DQS
t
RPST
Q
t
RPRE
t
DQSQmax
t
QH
t
QH
t
DQSQmax
Figure -- Data output (read) timing
Q
Q
Q
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5PS12421F-3 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421F-5 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421F-E3 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421FP 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421FP-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
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