參數(shù)資料
型號: HY5PS121621LF
廠商: Hynix Semiconductor Inc.
英文描述: 512Mb DDR2 SDRAM
中文描述: 512Mb DDR2 SDRAM芯片
文件頁數(shù): 27/35頁
文件大小: 624K
代理商: HY5PS121621LF
Rev. 1.0 / Feb. 2005
27
1
HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
V
DDQ
V
IH
(ac)min
V
IH
(dc)min
V
REF
(dc)
V
IL
(dc)max
V
IL
(ac)max
Vss
Delta TF
Delta TR
V
REF
to ac
region
nominal
slew rate
nominal
slew rate
t
IS
,
t
DS
V
REF
(dc)-V
IL
(ac)max
Delta TF
Setup Slew Rate
Falling Signal
=
V
IH
(ac)min-V
REF
(dc)
Delta TR
Setup Slew Rate
Rising Signal
=
t
IH
,
t
DH
t
IS
,
t
DS
t
IH
,
t
DH
CK, DQS
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