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參數(shù)資料
| 型號： | HY5DU56822BT-D |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256M-P DDR SDRAM |
| 中文描述： | 256M磷DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 233K |
| 代理商： | HY5DU56822BT-D |
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Rev. 0.4 / Aug. 2003 24
HY5DU56422BT-D4/ D43
HY5DU56822BT-D4/ D43
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
32Mx8
Parameter
Symbol
Test Condition
Speed
Unit
Note
-D4
-D43
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
130
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle;
IOUT=0mA
130
mA
Precharge Power Down
Standby Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing
once per clock cycle.
VIN=VREF for DQ, DQS and DM
60
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode ; CKE=Low,
tCK=tCK(min)
15
mA
Active Standby Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
65
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
190
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
210
mA
Auto Refresh Current
I
DD5
tRC=tRFC(min); All banks active
190
mA
Self Refresh Current
I
DD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
3
mA
Low Power
1.5
mA
Operating Current - Four
Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
290
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422CT-D | 256M-P DDR SDRAM |
| HY5DU561622CT-D4 | 256M-P DDR SDRAM |
| HY5DU561622CT-D43 | 256M-P DDR SDRAM |
| HY5DU56422CT-D4 | 256M-P DDR SDRAM |
| HY5DU56422CT-D43 | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56822BT-D4/D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56822CT-D | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56822CT-D4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56822CT-D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56822DLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM |
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