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Rev. 0.1 /May 2004 25
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
32Mx8
Parameter
Symbol
Test Condition
Speed
Unit Note
-J
-M
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
80
70
65
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
100
90
80
mA
Precharge Power
Down Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
50
40
30
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
15
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
45
40
35
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
160
150
130
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
160
150
130
mA
Auto Refresh Current
I
DD5
tRC=tRFC(min); All banks active
150
140
130
mA
Self Refresh Current
I
DD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
3
mA
Low Power
1.5
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
220
200
180
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DTP-M | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-X | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DLTP | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DLTP-H | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DLTP-J | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422DTP-M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mx4|2.5V|8K|K/H/L|DDR SDRAM - 256M |
| HY5DU56422LT-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X16MX4|CMOS|TSSOP|66PIN|PLASTIC |
| HY5DU56422LT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
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