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    參數(shù)資料
    型號: HY5DU56422DTP-H
    廠商: HYNIX SEMICONDUCTOR INC
    元件分類: DRAM
    英文描述: 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    中文描述: 64M X 4 DDR DRAM, 0.75 ns, PDSO66
    封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
    文件頁數(shù): 31/37頁
    文件大?。?/td> 414K
    代理商: HY5DU56422DTP-H
    Rev. 0.1 /May 2004 31
    HY5DU56422D(L)TP
    HY5DU56822D(L)TP
    HY5DU561622D(L)TP
    Input Setup Time (slow slew rate)
    t
    IS
    0.8
    -
    1.0
    -
    ns
    2,4,5,6
    Input Hold Time (slow slew rate)
    t
    IH
    0.8
    -
    1.0
    -
    ns
    Input Pulse Width
    t
    IPW
    2.2
    -
    2.2
    -
    ns
    6
    Write DQS High Level Width
    t
    DQSH
    0.35
    -
    0.35
    -
    CK
    Write DQS Low Level Width
    t
    DQSL
    0.35
    -
    0.35
    -
    CK
    Clock to First Rising edge of DQS-In
    t
    DQSS
    0.75
    1.25
    0.72
    1.28
    CK
    Data-In Setup Time to DQS-In (DQ & DM)
    t
    DS
    0.45
    -
    0.5
    -
    ns
    6,7,11,
    12,13
    Data-in Hold Time to DQS-In (DQ & DM)
    t
    DH
    0.45
    -
    0.5
    -
    ns
    DQ & DM Input Pulse Width
    t
    DIPW
    1.75
    -
    1.75
    -
    ns
    Read DQS Preamble Time
    t
    RPRE
    0.9
    1.1
    0.9
    1.1
    CK
    Read DQS Postamble Time
    t
    RPST
    0.4
    0.6
    0.4
    0.6
    CK
    Write DQS Preamble Setup Time
    t
    WPRES
    0
    -
    0
    -
    CK
    Write DQS Preamble Hold Time
    t
    WPREH
    0.25
    -
    0.25
    -
    CK
    Write DQS Postamble Time
    t
    WPST
    0.4
    0.6
    0.4
    0.6
    CK
    Mode Register Set Delay
    t
    MRD
    2
    -
    2
    -
    CK
    Exit Self Refresh to Any Execute Command
    t
    XSC
    200
    -
    200
    -
    CK
    8
    Average Periodic Refresh Interval
    t
    REFI
    -
    7.8
    -
    7.8
    us
    Parameter
    Symbol
    DDR333
    DDR266
    Unit
    Note
    Min
    Max
    Min
    Max
    相關(guān)PDF資料
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    HY5DU56422DTP-J 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    HY5DU56422DTP-K 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    HY5DU56422DTP-J 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    HY5DU56422DTP-K 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    HY5DU56422DTP-L 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    HY5DU56422DTP-M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
    HY5DU56422DTP-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)