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參數(shù)資料
| 型號： | HY5DU56422DLT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256Mb DDR SDRAM |
| 中文描述： | 256Mb的DDR SDRAM內存 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HY5DU56422DLT |
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Rev. 1.0 /Oct. 2004
26
HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
Note:
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock: A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This Derating Table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS): DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQ-
max, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-chan-
nel variation of the output drivers.
11. This Derating Table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12. I/O Setup/Hold Plateau Derating. This Derating Table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DT | 256Mb DDR SDRAM |
| HY5DU56822DLT | 256Mb DDR SDRAM |
| HY5DU56822DT | 256Mb DDR SDRAM |
| HY5DU56422BT-D4 | 256M-P DDR SDRAM |
| HY5DU56822BT-D | 256M-P DDR SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422DLTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-J | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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