參數(shù)資料
型號(hào)： HY5DU561622LT-K
英文描述： DDR Synchronous DRAM
中文描述： DDR同步DRAM
文件頁(yè)數(shù)： 27/37頁(yè)
文件大?。?/td> 336K
代理商： HY5DU561622LT-K
Rev. 0.3 / Dec. 01
27
HY5DU12422T
HY5DU12822T
HY5DU121622T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing
at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
相關(guān)PDF資料
PDF描述
HY5DU561622LT-L SDRAM|DDR|4X4MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU561622T 16Mx16|2.5V|8K|K/H/L|DDR SDRAM - 256M
HY5DU561622T-H DDR Synchronous DRAM
HY5DU561622T-K SDRAM|DDR|4X4MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU561622T-L DDR Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU561622LT-L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X4MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU561622T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx16|2.5V|8K|K/H/L|DDR SDRAM - 256M
HY5DU561622T-H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HY5DU561622T-K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X4MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU561622T-L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
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