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參數(shù)資料
| 型號(hào)： | HY5DU561622DT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256Mb DDR SDRAM |
| 中文描述： | 256Mb的DDR SDRAM內(nèi)存 |
| 文件頁(yè)數(shù)： | 27/29頁(yè) |
| 文件大小： | 236K |
| 代理商： | HY5DU561622DT |
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Rev. 1.0 /Oct. 2004
27
HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This Derating Table is used to increase tDS/tDH in case where the DQ and DQS
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns
and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi-
tions through the DC region must be monotonic.
15. tDAL = (tWR/tCK) + (tRP / tCK). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK.
17. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DLT | 256Mb DDR SDRAM |
| HY5DU56422DT | 256Mb DDR SDRAM |
| HY5DU56822DLT | 256Mb DDR SDRAM |
| HY5DU56822DT | 256Mb DDR SDRAM |
| HY5DU56422BT-D4 | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU561622DTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU561622DTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU561622DTP-J | 制造商:SK Hynix Inc 功能描述:SDRAM, DDR, 16M x 16, 66 Pin, Plastic, TSSOP |
| HY5DU561622DTP-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU561622DTP-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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