參數(shù)資料
型號(hào)： HY5DU28822BLT-J
英文描述： SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
中文描述： 內(nèi)存|復(fù)員| 4X4MX8 |的CMOS | TSSOP封裝| 66PIN |塑料
文件頁(yè)數(shù)： 3/37頁(yè)
文件大?。?/td> 336K
代理商： HY5DU28822BLT-J
DESCRIPTION
The Hynix HY5DU12422T, HY5DU12822T and HY5DU121622T are a 536,870,912-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high
bandwidth.
The Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable /CAS latency 2 and 2.5 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
Configuration
Power
HY5DU12422T-X*
128Mx4
Standard
HY5DU12422LT-X*
128Mx4
Low Power
HY5DU12822T-X*
64Mx8
Standard
HY5DU12822LT-X*
64Mx8
Low Power
HY5DU121622T-X*
32Mx16
Standard
HY5DU121622LT-X*
32Mx16
Low Power
HY5DU12422T
HY5DU12822T
HY5DU121622T
Rev. 0.3 / Dec. 01 3
OPERATING FREQUENCY
* X means speed grade
** JEDEC specification compliant
Grade
CL2
CL2.5
Remark**
- K
133MHz
133MHz
DDR266A
- H
125MHz
133MHz
DDR266B
- L
100MHz
125MHz
DDR200
PRELIMINARY
相關(guān)PDF資料
PDF描述
HY5DU28822BLT-K SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BLT-L SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BLT-M SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BT 16Mx8|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M
HY5DU28822BT-H SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU28822BLT-K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BLT-L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BLT-M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X4MX8|CMOS|TSSOP|66PIN|PLASTIC
HY5DU28822BLT-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M-S DDR SDRAM
HY5DU28822BT 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M-S DDR SDRAM
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