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參數(shù)資料
| 型號： | HY5DU12822BLTP |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 512Mb DDR SDRAM |
| 中文描述： | 產品512Mb DDR SDRAM |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 396K |
| 代理商： | HY5DU12822BLTP |
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DESCRIPTION
The HY5DU12422B(L)TP, HY5DU12822B(L)TP and HY5DU121622B(L)TP are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable /CAS latency 2 / 2.5 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
Lead-free package
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
HY5DU12422B(L)TP-X*
128Mx4
400mil 66pin
TSOP-II
(Lead-free)
HY5DU12822B(L)TP-X*
64Mx8
HY5DU121622B(L)TP-X*
32Mx16
Rev 0.1 / July 2003
3
OPERATING FREQUENCY
Grade
CL2
CL2.5
Remark
(CL-tRCD-tRP)
- J
133MHz
166MHz
DDR333 (2.5-3-3)
- M
133MHz
133MHz
DDR266 (2-2-2)
- K
133MHz
133MHz
DDR266A (2-3-3)
- H
100MHz
133MHz
DDR266B (2.5-3-3)
- L
100MHz
125MHz
DDR200 (2-2-2)
HY5DU12422B(L)TP
HY5DU12822B(L)TP
HY5DU121622B(L)TP
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DU12822BLTP-X | 512Mb DDR SDRAM |
| HY5DU12822BTP | 512Mb DDR SDRAM |
| HY5DU12822BTP-X | 150PF, 50V, 5%, CER, NPO, SMT 0805 |
| HY5DU12822CLTP-X | 512Mb DDR SDRAM |
| HY5DU121622C | 512Mb DDR SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU12822BLTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822BT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822BTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822BTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822C | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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