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參數(shù)資料
| 型號： | HY5DU12422B |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 512Mb DDR SDRAM |
| 中文描述： | 產(chǎn)品512Mb DDR SDRAM |
| 文件頁數(shù)： | 26/37頁 |
| 文件大小： | 396K |
| 代理商： | HY5DU12422B |
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Rev. 0.1 / May 2004
26
HY5DU12422B(L)TP
HY5DU12822B(L)TP
HY5DU121622B(L)TP
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
64Mx8
Parameter
Symbol
Test Condition
Speed
-K
Unit
Note
-J
-M
-H
-L
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle
140
130
120
120
100
mA
Operating Current
I
DD1
180
160
150
150
140
mA
Precharge Power
Down Standby
Current
Idle Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
I
DD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and
DM
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle.
VIN=VREF for DQ, DQS and DM
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
35
mA
Idle Standby
Current
I
DD2F
35
mA
Idle Quiet Standby
Current
I
DD2Q
25
mA
Active Power
Down
Standby Current
I
DD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
CKE =< 0.2V; External clock on;
tCK=tCK(min)
45
40
mA
Operating Current
I
DD4R
250
210
210
210
180
mA
Operating Current
I
DD4W
250
210
210
210
180
Auto Refresh
Current
I
DD5
280
260
260
260
240
Self Refresh
Current
Operating Current
- Four Bank
Operation
I
DD6
Normal
Low Power
5
mA
mA
2.5
I
DD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
460
380
380
380
300
mA
Random Read
Current
I
DD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
clock cycle
460
380
380
380
300
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU12422BLTP | 512Mb DDR SDRAM |
| HY5DU12422BLTP-X | 512Mb DDR SDRAM |
| HY5DU12422BTP | 512Mb DDR SDRAM |
| HY5DU12422BTP-X | 512Mb DDR SDRAM |
| HY5DU12822BLTP | 512Mb DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU12422BLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422BLTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422BLTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422BT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422BT_06 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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