參數(shù)資料
型號： HY5DU121622A
廠商： Hynix Semiconductor Inc.
英文描述： 512Mb DDR SDRAM
中文描述： 產(chǎn)品512Mb DDR SDRAM
文件頁數(shù)： 26/33頁
文件大?。?/td> 379K
代理商： HY5DU121622A
Rev. 0.0/Feb. 2003 26
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
32Mx16
Parameter
Symbol
Test Condition
Speed
Unit
Note
-D4
-D43
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
150
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
200
mA
Precharge Power
Down Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby Current
I
DD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per
clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Idle Quiet Standby
Current
I
DD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses
and other control inputs stable, Vin=Vref for DQ, DQS and
DM
25
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
50
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
280
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
330
Auto Refresh Current
I
DD5
tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
300
Self Refresh Current
I
DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
5
mA
Low Power
2.5
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
540
mA
Random Read
Current
I
DD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA,
100% DQ, DM and DQS inputs changing twice per clock
cycle; 100% addresses changing once per clock cycle
540
mA
相關(guān)PDF資料
PDF描述
HY5DU121622ALT-X 512Mb DDR SDRAM
HY5DU121622AT-X 512Mb DDR SDRAM
HY5DU12422A 512Mb DDR SDRAM
HY5DU12422ALT-X 512Mb DDR SDRAM
HY5DU12422AT-X 512Mb DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU121622ALT 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM
HY5DU121622ALT-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM
HY5DU121622AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32Mx16|2.5V|8K|J/M/K/H/L|DDR SDRAM - 512M
HY5DU121622ATP-J 制造商:SK Hynix Inc 功能描述:32M X 16 DDR DRAM, 0.7 ns, PDSO66
HY5DU121622AT-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM
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