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參數(shù)資料
| 型號： | HY57W2A1620HCLT-H |
| 英文描述： | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| 中文描述： | 內存| 4X2MX16 |的CMOS |的TSOP | 54PIN |塑料 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | HY57W2A1620HCLT-H |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
23
Deep Power Down Mode (Continued)
Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command.
1. Maintain NOP input conditions for a minimum of 200
μ
sec
2. Issue precharge commands for all banks of the device
3. Issue 8 or more auto refresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down mode exit sequence.
CLK
CKE
CS
RAS
CAS
WE
Deep Power Down
exit
All banks
precharge
Auto
refresh
Auto
refresh
Mode
Register
Set
Extended
Mode
Register
Set
New
Command
Accepted
Here
200
μ
s
tRP
tRC
相關PDF資料 |
PDF描述 |
|---|---|
| HY57W2A1620HCLT-P | x16 SDRAM |
| HY57W2A1620HCLT-S | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-B | x16 SDRAM |
| HY57W2A1620HCST-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-P | x16 SDRAM |
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