參數(shù)資料
型號(hào): HY57V651620BTC-55
廠商: HYNIX SEMICONDUCTOR INC
元件分類(lèi): DRAM
英文描述: 4 Banks x 1M x 16Bit Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 81K
代理商: HY57V651620BTC-55
HY57V651620B
Rev. 1.9/Apr.01
9
DEVICE OPERATING OPTION TABLE
HY57V651620B(L)TC-55
HY57V651620B(L)TC-6
HY57V651620B(L)TC-7
HY57V651620B(L)TC-75
HY57V651620B(L)TC-8
HY57V651620B(L)TC-10P
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
183MHz(6ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
166MHz(7ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
143MHz(7ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
166MHz(6ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
143MHz(7ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
133MHz(7.5ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
3 C L K s
5.4ns
2.7ns
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
143MHz(7ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
5.4ns
2.7ns
133MHz(7.5ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
3 C L K s
5.4ns
2.7ns
125MHz(8ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
2 C L K s
6 n s
3 n s
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
133MHz(7.5ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
3 C L K s
5.4ns
2.7ns
125MHz(8ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
3 C L K s
6 n s
3 n s
100MHz(10ns)
2 C L K s
2CLKs
5 C L K s
7CLKs
2 C L K s
6 n s
3 n s
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
125MHz(8ns)
3 C L K s
3CLKs
7 C L K s
10CLKs
3 C L K s
6 n s
3 n s
100MHz(10ns)
2 C L K s
2CLKs
5 C L K s
7CLKs
3 C L K s
6 n s
3 n s
83MHz(12ns)
3 C L K s
3CLKs
6 C L K s
9CLKs
2 C L K s
6 n s
3 n s
C A S Latency
t R C D
t R A S
tRC
tRP
t A C
t O H
100MHz(10ns)
2 C L K s
2CLKs
5 C L K s
7CLKs
2 C L K s
6 n s
3 n s
83MHz(12ns)
2 C L K s
2CLKs
5 C L K s
7CLKs
2 C L K s
6 n s
3 n s
66MHz(15ns)
2 C L K s
2CLKs
4 C L K s
6CLKs
2 C L K s
6 n s
3 n s
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