參數(shù)資料
型號: HY57V64820HGTP
廠商: Hynix Semiconductor Inc.
英文描述: 4 Banks x 2M x 8Bit Synchronous DRAM
中文描述: 4銀行x 2米× 8位同步DRAM
文件頁數(shù): 10/11頁
文件大?。?/td> 134K
代理商: HY57V64820HGTP
HY57V64820HG
Rev. 0.5/Sep. 02
10
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-READ-Single-WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge
power down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
相關(guān)PDF資料
PDF描述
HY57V64820HGLT-7 4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGLT-8 4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGLT-H CAP 0.01UF 50V 5% X7R SMD-0805 TR-7 PLATED-NI/SN
HY57V64820HGLT-K 4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGLT-P 4 Banks x 2M x 8Bit Synchronous DRAM
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