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參數(shù)資料
| 型號(hào)： | HY57V64820HGLT |
| 英文描述： | 8Mx8|3.3V|4K|6|SDR SDRAM - 64M |
| 中文描述： | 8Mx8 | 3.3 | 4K的| 6 | SDRAM的特別提款權(quán)- 64米 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 61K |
| 代理商： | HY57V64820HGLT |
HY57V281620A
Rev. 1.3/Aug. 01
3
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V64820HGT | 8Mx8|3.3V|4K|6|SDR SDRAM - 64M |
| HY57V651610TC-10 | x16 SDRAM |
| HY57V651610TC-12 | x16 SDRAM |
| HY57V654020BLTC-75 | x4 SDRAM |
| HY57V654020BLTC-8 | x4 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V64820HGLT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
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