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參數(shù)資料
| 型號： | HY57V64820HGLT-8 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 2M x 8Bit Synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 134K |
| 代理商： | HY57V64820HGLT-8 |
HY57V64820HG
Rev. 0.5/Sep. 02
6
DC CHARACTERISTICS II
(TA=0 to 70
°
C
, V
DD
=3.3
±
0.3V, V
SS
=0V)
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V64820HGT-7/K/H/8/P/S
4.HY57V64820HGLT-7/K/H/8/P/S
Parameter
Symbol
Test Condition
Speed
Unit
Note
-6
-7
-K
-H
-8
-P/S
Operating Current
I
DD1
Burst length=1, One bank active
t
RC
≥
t
RC
(min), I
OL
=0mA
90
85
85
85
85
80
mA
1
Precharge Standby Current
in Power Down Mode
I
DD2P
CKE
≤
V
IL
(max), t
CK
= min
2
mA
I
DD2PS
CKE
≤
V
IL
(max), t
CK
=
∞
2
mA
Precharge Standby Current
in Non Power Down Mode
I
DD2N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= min
Input signals are changed one time during
2clks. All other pins
≥
V
DD
-0.2V or
≤
0.2V
15
mA
I
DD2NS
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
12
mA
Active Standby Current
in Power Down Mode
I
DD3P
CKE
≤
V
IL
(max), t
CK
= min
6
mA
I
DD3PS
CKE
≤
V
IL
(max), t
CK
=
∞
5
mA
Active Standby Current
in Non Power Down Mode
I
DD3N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= min
Input signals are changed one time during
2clks. All other pins
≥
V
DD
-0.2V or
≤
0.2V
30
mA
I
DD3NS
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
20
mA
Burst Mode Operating Current
I
DD4
t
CK
≥
t
CK
(min), I
OL
=0mA
All banks active
CL=3
150
150
150
150
130
120
mA
1
CL=2
NA
NA
120
mA
Auto Refresh Current
I
DD5
t
RRC
≥
t
RRC
(min), All banks active
160
mA
2
Self Refresh Current
I
DD6
CKE
≤
0.2V
1
mA
3
400
uA
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V64820HGLT-H | CAP 0.01UF 50V 5% X7R SMD-0805 TR-7 PLATED-NI/SN |
| HY57V64820HGLT-K | 4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-P | 4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-S | 4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLTP-5 | 4 Banks x 2M x 8Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V64820HGLT-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLT-P | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLTP-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
| HY57V64820HGLTP-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 8Bit Synchronous DRAM |
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