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參數(shù)資料
| 型號： | HY57V28820HCT-KI |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4Banks x 4M x 8bits Synchronous DRAM |
| 中文描述： | 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 175K |
| 代理商： | HY57V28820HCT-KI |
HY57V28820HC(L)T-I
Rev. 0.1/Jan. 01
2
PIN CONFIGURATION
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V28820HCT-PI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCT-SI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V561620B | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620BLT-6I | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620BLT-8I | 4 Banks x 4M x 16Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V28820HCT-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HY57V28820HCT-PI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCT-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HY57V28820HCT-SI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
| HY57V561620 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 16Bit Synchronous DRAM |
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