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參數(shù)資料
| 型號(hào)： | HY57V28820BLT |
| 英文描述： | 16Mx8|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M |
| 中文描述： | 16Mx8 | 3.3 | 4K的| 6/K/H/8/P/S |特別提款權(quán)的SDRAM - 128M的 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 61K |
| 代理商： | HY57V28820BLT |
HY57V281620A
Rev. 1.3/Aug. 01
13
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
′
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-Single-
WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
MRS
Mode
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge
power down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V28820BT | 16Mx8|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M |
| HY57V28820HCLT | 16Mx8|3.3V|4K|6|SDR SDRAM - 128M |
| HY57V28820HCLT-6 | x8 SDRAM |
| HY57V28820HCLT-8 | x8 SDRAM |
| HY57V28820HCLT-H | x8 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V28820BT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx8|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M |
| HY57V28820HCLT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx8|3.3V|4K|6|SDR SDRAM - 128M |
| HY57V28820HCLT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HY57V28820HCLT-6I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
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