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參數(shù)資料
| 型號： | HY57V283220LTP-S |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 1M x 32Bit Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 916K |
| 代理商： | HY57V283220LTP-S |
Rev. 0.9 / July 2004
9
HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Parameter
Symbol
-5
-55
-6
-7
-H
-8
-P
-S
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System clock
cycle time
CAS Latency = 3
tCK3
5
1000
5.5
1000
6
1000
7
1000
7.5
1000
8
1000
10
1000
10
1000
ns
CAS Latency = 2
tCK2
10
10
10
10
10
-10
10
12
ns
Clock high pulse width
tCHW
2
-
2.25
-
2.5
-
3
-
3
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2
-
2.25
-
2.5
-
3
-
3
-
3
-
3
-
3
-
ns
1
Access time from
clock
CAS Latency = 3
tAC3
-
4.5
-
5
-
5.5
-
5.5
-
5.5
-
6
-
6
-
6
ns
2
CAS Latency = 2
tAC2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6
ns
Data-out hold time
tOH
1.5
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
ns
3
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.75
-
1.75
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.75
-
1.75
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.75
-
1.75
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.75
-
1.75
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
CLK to data output
in high Z-time
CAS Latency = 3
tOHZ3
-
4.5
-
5
-
5.5
-
5.5
-
5.5
-
6
-
6
-
6
ns
CAS Latency = 2
tOHZ2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6
ns
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V283220LT-S | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-5 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-55 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-6 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-7 | 4 Banks x 1M x 32Bit Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V283220LT-S | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
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