參數(shù)資料
型號(hào): HY57V283220LT-7I
廠商: HYNIX SEMICONDUCTOR INC
元件分類(lèi): DRAM
英文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
文件頁(yè)數(shù): 9/14頁(yè)
文件大?。?/td> 292K
代理商: HY57V283220LT-7I
Rev. 0.6/Nov. 02
4
HY57V283220T-I / HY5V22F-I
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
X
d
e
co
d
er
S
tate
M
a
ch
in
e
A0
A1
A11
BA0
BA1
A
d
dr
es
sbu
ffe
rs
Address
Register
Mode Register
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Row Active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Refresh
Counter
DQ0
DQ1
DQ30
DQ31
Self Refresh Logic
& Timer
Pipe Line Control
I/O
B
u
ffer
&
Logic
Bank Select
Se
nse
AM
P
&
I/O
Ga
te
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
x32 Bank 3
X
de
co
de
r
X
de
co
de
r
Memory
Cell
Array
Y decoder
X
d
e
code
r
1M x32 Bank 0
1M x32 Bank 1
1M x32 Bank 2
1M
X
d
e
co
d
er
X
d
e
co
d
er
S
tate
M
a
ch
in
e
A0
A1
A11
BA0
BA1
A
d
dr
es
sbu
ffe
rs
Address
Register
Mode Register
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Row Active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Refresh
Counter
DQ0
DQ1
DQ30
DQ31
Self Refresh Logic
& Timer
Pipe Line Control
I/O
B
u
ffer
&
Logic
Bank Select
Se
nse
AM
P
&
I/O
Ga
te
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
x32 Bank 3
X
de
co
de
r
X
de
co
de
r
X
de
co
de
r
X
de
co
de
r
Memory
Cell
Array
Y decoder
X
d
e
code
r
Memory
Cell
Array
Y decoder
X
d
e
code
r
1M x32 Bank 0
1M x32 Bank 1
1M x32 Bank 2
1M
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HY57V283220LT-P 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LTP-5 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LTP-55 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM